Along with improvement in performance of information processing apparatuses such as devices for communication trunk and servers, a high data rate in transmission/reception of signals in the inside and outside of the devices is demanded. A higher bit rate is desired in the field of high-speed I/O in which signals are transmitted and received in an integrated circuit chip, between chips (in a device, between devices) and the field of optical communications, for example.
A reception circuit is requested to determine transmitted data at a right timing and recover data and a clock (Clock and Data Recovery: CDR). The CDR is implemented by detecting a phase difference and a frequency difference between the input data and the received (sampling) clock, and performing phase adjustment on the sampling clock based on the detected information. Among the reception circuits, known is a CDR circuit that is retimed by a clock recovered from input data without using a reference clock and outputs data in which jitter is decreased.
In the CDR circuits, known is the use of a phase detector (PD) that detects a phase difference between input data and a clock. The CDR circuit is controlled such that the phases and the frequencies of the input data and a first clock respectively match each other, based on the phase difference detected by the phase detector. A state where the frequencies match each other is called a locked state. Further, a state that is not the locked state is herein called an unlocked state.
Related art are disclosed in Japanese Laid-open Patent Publication Nos. 2002-198808, 2002-135093, 2014-187561, and 9-147499. In addition, Related art are disclosed in Ansgar Pottbacker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, December 1992 (hereinafter, referred to as “Non-patent document 1”).